Synchronization; Table 48. Positioning Of Captured Data Bytes In 32-Bit Words (12-Bit Width); Table 49. Positioning Of Captured Data Bytes In 32-Bit Words (14-Bit Width) - ST STM32F205 series Reference Manual

Digital camera interface (DCMI)
12-bit data
When EDM[1:0] in DCMI_CR are programmed to "10", the camera interface captures the
12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in

Table 48. Positioning of captured data bytes in 32-bit words (12-bit width)

Byte address
0
4
14-bit data
When EDM[1:0] in DCMI_CR are programmed to "11", the camera interface captures the
14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in

Table 49. Positioning of captured data bytes in 32-bit words (14-bit width)

Byte address
0
4
12.5.3

Synchronization

The digital camera interface supports embedded or hardware (HSYNC & VSYNC)
synchronization. When embedded synchronization is used, it is up to the digital camera
module to make sure that the 0x00 and 0xFF values are used ONLY for synchronization
(not in data). Embedded synchronization codes are supported only for the 8-bit parallel data
interface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to
"00").
For compressed data, the DCMI supports only the hardware synchronization mode. In this
case, VSYNC is used as a start/end of the image, and HSYNC is used as a Data Valid
signal. Figure 59
282/1378
31:28
0
0
31:30
0
0
shows the corresponding timing diagram.
RM0033 Rev 8
27:16
D [11:0]
n+1
D [11:0]
n+3
29:16
D [13:0]
n+1
D [13:0]
n+3
nd
Table
15:12 11:0
0 D [11:0]
n
0 D [11:0]
n+2
nd
Table
15:14 13:0
0 D [13:0]
n
0 D [13:0]
n+2
RM0033
48.
49.