Figure 186. Counter Timing Diagram, Internal Clock Divided By 2; Figure 187. Counter Timing Diagram, Internal Clock Divided By 4; Figure 188. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F207 Series Reference Manual

Basic timers (TIM6 and TIM7)
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Figure 186. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 187. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 188. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
0034 0035 0036
0035 0036
1F 20
RM0033 Rev 9
0000 0001 0002 0003
0000 0001
MSv37301V1
00
RM0033
MS35835V1
MSv37302V1