Figure 24. Peripheral-To-Memory Mode - ST STM32F207 Series Reference Manual

RM0033
DMA controller
REQ_STREAMx
1. For double-buffer mode.
Memory-to-peripheral mode
Figure 25
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into
the destination. When the level of the FIFO is lower than or equal to the predefined
threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold
level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to
transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA
transfers the preloaded value into the configured destination. It then reloads again the
empty internal FIFO with the next data to be transfer. The preloaded data size corresponds
to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.

Figure 24. Peripheral-to-memory mode

FIFO
Arbiter
level
describes this mode.
DMA_SxM0AR
DMA_SxM1AR (1)
AHB memory
port
FIFO
AHB peripheral
port
DMA_SxPAR
Peripheral DMA request
RM0033 Rev 9
DMA controller (DMA)
Memory bus
Memory
destination
Peripheral bus
Peripheral
source
MS47543V1
183/1381
211