Ieee 1588 Time Stamp Registers - ST STM32F207 Series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MMC received frames with alignment error counter register
(ETH_MMCRFAECR)
Address offset: 0x0198
Reset value: 0x0000 0000
This register contains the number of frames received with alignment (dribble) error.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 RFAEC: Received frames alignment error counter
MMC received good unicast frames counter register (ETH_MMCRGUFCR)
Address offset: 0x01C4
Reset value: 0x0000 0000
This register contains the number of good unicast frames received.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 RGUFC: Received good unicast frames counter
28.8.3

IEEE 1588 time stamp registers

This section describes the registers required to support precision network clock
synchronization functions under the IEEE 1588 standard.
Ethernet PTP time stamp control register (ETH_PTPTSCR)
Address offset: 0x0700
Reset value: 0x0000 00002000
This register controls the time stamp generation and update logic.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
932/1381
r r r r r r
Received frames with alignment error counter
r r r r r r
RFAEC
r r r r r r r
RGUFC
r r r r r r r
rw rw rw rw rw rw rw rw rw rw
RM0033 Rev 9
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
rw rw rw rw rw rw
RM0033
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r
4 3 2 1 0