Table 199. Programmable Nand/Pc Card Access Parameters; Table 200. 8-Bit Nand Flash - ST STM32F207 Series Reference Manual

Flexible static memory controller (FSMC)
Parameter
Memory setup
time
Memory wait
Memory hold
Memory
databus high-Z
31.6.1 External memory interface signals
The following tables list the signals that are typically used to interface NAND Flash and PC
Card.
Note: Prefix "N". specifies the associated signal as active low.
8-bit NAND Flash
t
FSMC signal name
A[17]
A[16]
D[7:0]
NCE[x]
NOE(= NRE)
NWE
NWAIT/INT[3:2]
There is no theoretical capacity limitation as the FSMC can manage as many address
cycles as needed.
1302/1381

Table 199. Programmable NAND/PC Card access parameters

Function
Number of clock cycles (HCLK)
to set up the address before the
command assertion
Minimum duration (HCLK clock
cycles) of the command assertion
Number of clock cycles (HCLK)
to hold the address (and the data
in case of a write access) after
the command de-assertion
Number of clock cycles (HCLK)
during which the databus is kept
in high-Z state after the start of a
write access

Table 200. 8-bit NAND Flash

I/O
O NAND Flash address latch enable (ALE) signal
O NAND Flash command latch enable (CLE) signal
I/O 8-bit multiplexed, bidirectional address/data bus
O Chip select, x = 2, 3
O Output enable (memory signal name: read enable, NRE)
O Write enable
I NAND Flash ready/busy input signal to the FSMC
RM0033 Rev 9
Access mode Unit
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Write
(HCLK)
Function
RM0033
Min. Max.
1 255
2 256
1 254
0 255