Timing Diagram; Analog Watchdog; Figure 29. Timing Diagram; Figure 30. Analog Watchdog's Guarded Area - ST STM32F205 series Reference Manual

Analog-to-digital converter (ADC)
Note: Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to
10.3.6

Timing diagram

As shown in
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
ADC_CLK
ADON
SWSTART/
JSWSTART
ADC
EOC
10.3.7

Analog watchdog

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 33
watchdog on one or more channels.
216/1378
Figure 29, the ADC needs a stabilization time of t

Figure 29. Timing diagram

Start 1st conversion
ADC conversion
Conversion time
t STAB
(total conv. time)
shows how the ADC_CR1 register should be configured to enable the analog

Figure 30. Analog watchdog's guarded area

Analog voltage
Higher threshold
Lower threshold
Auto-injection section)
Software clears the EOC bit
Guarde d area
RM0033 Rev 8
.
before it starts
STAB
Start next conversion
Next ADC conversion
HTR
LT R
ai16048
RM0033
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