Figure 129. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 130. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F207 Series Reference Manual

RM0033 General-purpose timers (TIM2 to TIM5)

Figure 129. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register 0034 0035 0036 0035
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)
MS37344V1
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 130. Counter timing diagram, internal clock divided by N

CK_INT
Timerclock = CK_CNT
Counter register
20 1F 01 00
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
MS37345V1
RM0033 Rev 9 387/1381
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