Supported Memories And Transactions; Table 177. Multiplexed I/O Psram; Table 178. Nor Flash/Psram Controller: Example Of Supported Memories And Transactions - ST STM32F207 Series Reference Manual

RM0033
FSMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
31.5.2

Supported memories and transactions

Table 178
transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.
Transactions not allowed (or not supported) by the FSMC in this example appear in gray.

Table 178. NOR Flash/PSRAM controller: example of supported memories and transactions

Device
Asynchronous
Asynchronous
Asynchronous
Asynchronous
NOR Flash
Asynchronous
(muxed I/Os and
Asynchronous
nonmuxed I/Os)
Asynchronous page
Synchronous
Synchronous
Synchronous

Table 177. Multiplexed I/O PSRAM

I/O
O Clock (for synchronous access)
O Address bus
I/O 16-bit multiplexed, bidirectional address/data bus
O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O Output enable
O Write enable
O Address valid PSRAM input (memory signal name: NADV)
I PSRAM wait input signal to the FSMC
O Upper byte enable (memory signal name: NUB)
O Lowed byte enable (memory signal name: NLB)
below displays an example of the supported devices, access modes and
Mode R/W
R
W
R
W
R
W
R
R
R
R
Flexible static memory controller (FSMC)
AHB Allowed/
Memory
data
data size
size allowed
8 16
8 16
16 16
16 16
32 16
32 16
- 16
8 16
16 16
32 16
RM0033 Rev 9
Function
not Comments
Y -
N -
Y -
Y -
Y Split into two FSMC accesses
Y Split into two FSMC accesses
N Mode is not supported
N -
Y -
Y -
1269/1381
1318