Table 15. Flexible Swj-Dp Pin Assignment - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus
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General-purpose I/Os (GPIO)
Full SWJ (JTAG-DP + SW-DP) - Reset state
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
JTAG-DP Disabled and SW-DP Enabled
JTAG-DP Disabled and SW-DP Disabled
GPIO
Configure the desired I/O as output or input in the GPIOx_MODER register.
Peripheral alternate function
For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER
register.
For other peripherals:
EVENTOUT
Configure the I/O pin used to output the Cortex
it to AF15
Note:
EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0, PH1 and
PI8.
Please refer to the "Alternate function mapping" table in the datasheets for the detailed
mapping of the system and peripherals' alternate function I/O pins.
142/1378

Table 15. Flexible SWJ-DP pin assignment

Available debug ports
Configure the desired I/O as an alternate function in the GPIOx_MODER register
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively
Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register
PA13 /
JTMS/
SWDIO
X
X
X
®
-M3 EVENTOUT signal by connecting
RM0033 Rev 8
SWJ I/O pin assigned
PA14 /
PA15 /
PB3 /
JTCK/
JTDI
JTDO
SWCLK
X
X
X
X
X
X
X
Released
RM0033
PB4/
NJTRST
X

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