Spi Functional Description; General Description; Figure 248. Spi Block Diagram - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

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SPI functional description

The block diagram of the SPI is shown in

Usually, the SPI is connected to external devices through four pins:

MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode

and receive data in master mode.

MOSI: Master Out / Slave In data. This pin can be used to transmit data in master

mode and receive data in slave mode.

SCK: Serial Clock output for SPI masters and input for SPI slaves.

NSS: Slave select. This is an optional pin to select a slave device. This pin acts as a

'chip select' to let the SPI master communicate with slaves individually and to avoid

contention on the data lines. Slave NSS inputs can be driven by standard IO ports on

the master device. The NSS pin may also be used as an output if enabled (SSOE bit)

and driven low if the SPI is in master configuration. In this manner, all NSS pins from

devices connected to the Master NSS pin see a low level and become slaves when

they are configured in NSS hardware mode. When configured in master mode with

NSS configured as an input (MSTR=1 and SSOE=0) and if NSS is pulled low, the SPI

enters the master mode fault state: the MSTR bit is automatically cleared and the

device is configured in slave mode (refer to

A basic example of interconnections between a single master and a single slave is

illustrated in

Shift register

Baud rate generator

Master control logic

RM0033 Rev 9

Address and data bus

Communication control

Serial peripheral interface (SPI)

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