RM0033
–
•
Gate HCLK (GATEHCLK bit in OTG_HS_PCGCCTL)
When setting the Gate HCLK bit in the clock gating control register, most of the system
clock domain internal to the OTG_HS core is switched off by clock gating. Only the
register read and write interface is kept alive. The dynamic power consumption due to
the USB clock switching activity is cut even if the system clock is kept running by the
application for other purposes.
•
USB system stop
–
–
30.9
Dynamic update of the OTG_HS_HFIR register
The USB core embeds a dynamic trimming capability of micro-SOF framing period in host
mode allowing to synchronize an external device with the micro-SOF frames.
When the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF
period correction is applied in the next frame as described in
SOF
reload
OTG_HS_HFIR
write
OTG_HS_HFIR
value
Frame
timer
The dynamic power consumption due to the USB clock switching activity is cut
even if the clock input is kept running by the application
Most of the transceiver is also disabled, and only the part in charge of detecting
the asynchronous resume or remote wakeup event is kept alive.
When the OTG_HS is in USB suspended state, the application can decide to
drastically reduce the overall power consumption by shutting down all the clock
sources in the system. USB System Stop is activated by first setting the Stop PHY
clock bit and then configuring the system deep sleep mode in the powercontrol
system module (PWR).
The OTG_HS core automatically reactivates both system and USB clocks by
asynchronous detection of remote wakeup (as an host) or resume (as a Device)
signaling on the USB.
Figure 376. Updating OTG_HS_HFIR dynamically
Old OTG_HS_HIFR value
= 400 periods
400
...
USB on-the-go high-speed (OTG_HS)
OTG_HS_HIFR value
= 450 periods+HIFR write latency
Latency
450
...
...
RM0033 Rev 9
Figure
376.
New OTG_HS_HIFR value
= 450 periods
...
1115/1381
...
ai18439b
1260
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