Figure 276. Operations Required To Transmit 0X3478Ae; Figure 277. Operations Required To Receive 0X3478Ae; Figure 278. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0 - ST STM32F207 Series Reference Manual

Serial peripheral interface (SPI)
•
In reception mode:
If data 0x3478AE are received, two successive read operations from SPI_DR are
required on each RXNE event.

Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

CK
WS
SD
When 16-bit data frame extended to 32-bit channel frame is selected during the I
configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds
to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in
714/1381

Figure 276. Operations required to transmit 0x3478AE

First write to Data register
conditioned by TXE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.

Figure 277. Operations required to receive 0x3478AE

First read from Data register
conditioned by RXNE=1
0xXX34
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
16-bit data
0 forced
MSB
Channel left 32-bit
Figure 279 is required.
RM0033 Rev 9
Second write to Data register
conditioned by TXE=1
0x78AE
Second read from Data register
conditioned by RXNE=1
0x78AE
Reception
Transmission
16-bit remaining
LSB
RM0033
MS19596V1
MS19597V1
Channel right
MS30105V1
2
S