Table 190. Fsmc_Bcrx Bit Fields; Figure 409. Mode D Write Accesses - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus
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Flexible static memory controller (FSMC)
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit No.
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
1282/1381

Figure 409. Mode D write accesses

Table 190. FSMC_BCRx bit fields

Bit name
Reserved
0x000
CBURSTRW
0x0 (no effect on asynchronous mode)
CPSIZE
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
ASYNCWAIT
at 0.
EXTMOD
0x1
WAITEN
0x0 (no effect on asynchronous mode)
WREN
As needed
WAITCFG
Don't care
WRAPMOD
0x0
WAITPOL
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
Set according to memory support
MWID
As needed
RM0033 Rev 9
Value to set
RM0033

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