Single-Wire Half-Duplex Communication; Figure 236. Usart Data Clock Timing Diagram (M=1); Figure 237. Rx Data Setup/Hold Time - ST STM32F207 Series Reference Manual

RM0033
Clock (CPOL=0,
CPHA=0
Clock (CPOL=0,
CPHA=1
Clock (CPOL=1,
CPHA=0
Clock (CPOL=1,
CPHA=1
Data on TX
(from master)
Data on RX
(from slave)
Capture
strobe
(capture strobe on CK rising
Data on RX (from slave)
t
SETUP=
Note: The function of CK is different in Smartcard mode. Refer to the Smartcard mode chapter for
more details.
24.3.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in USART_CR3).
Universal synchronous asynchronous receiver transmitter (USART)

Figure 236. USART data clock timing diagram (M=1)

Idle or
preceding Start
transmission
0
Start LSB
0
LSB

Figure 237. RX data setup/hold time

CK
edge in this example)
t 1/16 bit time
HOLD
M=1 (9 data bits)
1 2 3 4
1 2 3 4
Valid DATA bit
t
SETUP
RM0033 Rev 9
Stop
*
*
*
*
5 6 7 8
MSB
5 6 8
7
MSB
*
*LBCL bit controls last data pulse
t
HOLD
Idle or next
transmission
Stop
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