Dcmi Interrupt Clear Register (Dcmi_Icr) - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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DCMI interrupt clear register (DCMI_ICR)

Address offset: 0x14

Reset value: 0x0000 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

The DCMI_ICR register is write-only. Writing a '1' into a bit of this register clears the

corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a '0' has no effect.

Bits 15:5 Reserved, must be kept at reset value.

Bit 4 LINE_ISC: line interrupt status clear

Writing a '1' into this bit clears LINE_RIS in the DCMI_RIS register

Bit 3 VSYNC_ISC: Vertical synch interrupt status clear

Writing a '1' into this bit clears the VSYNC_RIS bit in DCMI_RIS

Bit 2 ERR_ISC: Synchronization error interrupt status clear

Writing a '1' into this bit clears the ERR_RIS bit in DCMI_RIS

Note: This bit is available only in embedded synchronization mode.

Bit 1 OVR_ISC: Overrun interrupt status clear

Writing a '1' into this bit clears the OVR_RIS bit in DCMI_RIS

Bits 0 FRAME_ISC: Capture complete interrupt status clear

Writing a '1' into this bit clears the FRAME_RIS bit in DCMI_RIS

RM0033 Rev 8

Digital camera interface (DCMI)

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