Hash Status Register (Hash_Sr) - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus

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Hash processor (HASH)

HASH status register (HASH_SR)

Address offset: 0x24

Reset value: 0x0000 0001

Bits 31:4 Reserved, forced by hardware to 0.

Bit 3 BUSY: Busy bit

0: No block is currently being processed

1: The hash core is processing a block of data

Bit 2 DMAS: DMA Status

This bit provides information on the DMA interface activity. It is set with DMAE

and cleared when DMAE=0 and no DMA transfer is ongoing. No interrupt is

associated with this bit.

0: DMA interface is disabled (DMAE=0) and no transfer is ongoing

1: DMA interface is enabled (DMAE=1) or a transfer is ongoing

Bit 1 DCIS: Digest calculation completion interrupt status

This bit is set by hardware when a digest becomes ready (the whole message

has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1

in the HASH_CR register.

0: No digest available in the HASH_Hx registers

1: Digest calculation complete, a digest is available in the HASH_Hx registers.

An interrupt is generated if the DCIE bit is set in the HASH_IMR register.

Bit 0 DINIS: Data input interrupt status

This bit is set by hardware when the input buffer is ready to get a new block (16

locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN

0: Less than 16 locations are free in the input buffer

1: A new block can be entered into the input buffer. An interrupt is generated if

the DINIE bit is set in the HASH_IMR register.

RM0033 Rev 9

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