Interrupts; Option Bytes; Description Of User Option Bytes; Table 5. Flash Interrupt Requests - ST STM32F205 Programming Manual

Flash memory interface
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the FLASH_CR register.
Note: The I/D cache should be flushed only when it is disabled (I/DCEN = 0).
2.5.5

Interrupts

Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program or erase operation request, one of the following error
flags is set in the FLASH_SR register:
•
PGAERR, PGPERR, PGSERR (Program error flags)
•
WRPERR (Protection error flag)
In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_SR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Refer to
Interrupt events
End of operation
Write protection error
Programming error
2.6

Option bytes

2.6.1

Description of user option bytes

The option bytes are configured by the end user depending on the application requirements.
shows the organization of these bytes inside the user configuration sector.
Table 6
Address
0x1FFF C000
0x1FFF C008
14/29
Table 5: Flash interrupt requests

Table 5. Flash interrupt requests

Table 6. Option byte organization

for summary of Flash interrupt request.
Event flags
EOP
WRPERR
PGAERR, PGPERR, PGSERR
[63:16]
Reserved ROP & user option bytes (RDP & USER)
Reserved
DocID15687 Rev 5
Enable control bits
EOPIE
ERRIE
ERRIE
[15:0]
Write protections nWRP
PM0059