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I7-900 DEKSTOP SPECIFICATION
INTEL I7-900 DEKSTOP SPECIFICATION Manuals
Manuals and User Guides for INTEL I7-900 DEKSTOP SPECIFICATION. We have
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INTEL I7-900 DEKSTOP SPECIFICATION manuals available for free PDF download: Datasheet, Specification
INTEL I7-900 DEKSTOP SPECIFICATION Datasheet (98 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 0.56 MB
Table of Contents
Table of Contents
3
Revision History
9
1 Introduction
11
Terminology
11
Processor Terminology
11
References
13
2 Register Description
15
Register Terminology
15
Platform Configuration Structure
16
Device Mapping
17
Functions Specifically Handled by the Processor
17
Detailed Configuration Space Maps
18
Device 0, Function 0: Generic Non-Core Registers
18
Device 0, Function 1: System Address Decoder Registers
19
Device 2, Function 0: Intel QPI Link 0 Registers
20
Device 2, Function 1: Intel QPI Physical 0 Registers
21
Device 3, Function 0: Integrated Memory Controller Registers
22
Device 3, Function 1: Target Address Decoder Registers
23
Device 4, Function 0: Integrated Memory Controller Channel
24
Control Registers
24
Device 4, Function 1: Integrated Memory Controller Channel
25
Address Registers
25
Device 4, Function 2: Integrated Memory Controller Channel
26
Rank Registers
26
Device 4, Function 3: Integrated Memory Controller Channel
27
Thermal Control Registers
27
Device 5, Function 0: Integrated Memory Controller Channel
28
Control Registers
28
Device 5, Function 1: Integrated Memory Controller Channel
29
Address Registers
29
Device 5, Function 2: Integrated Memory Controller Channel
30
Rank Registers
30
Device 5, Function 3: Integrated Memory Controller Channel
31
Thermal Control Registers
31
Device 6, Function 0: Integrated Memory Controller Channel
32
Control Registers
32
Device 6, Function 1: Integrated Memory Controller Channel
33
Address Registers
33
Device 6, Function 2: Integrated Memory Controller Channel
34
Rank Registers
34
Device 6, Function 3: Integrated Memory Controller Channel
35
Thermal Control Registers
35
PCI Standard Registers
36
VID - Vendor Identification Register
36
DID - Device Identification Register
36
RID - Revision Identification Register
37
CCR - Class Code Register
37
HDR - Header Type Register
38
SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register
38
PCICMD - Command Register
39
PCISTS - PCI Status Register
40
SAD - System Address Decoder Registers
41
Sad_Pam0123
41
Sad_Pam456
43
Sad_Hen
44
Sad_Smram
44
Sad_Pciexbar
45
Sad_Dram_Rule_0, Sad_Dram_Rule_1, Sad_Dram_Rule_2
45
Sad_Dram_Rule_3
45
Sad_Dram_Rule_4, Sad_Dram_Rule_5
45
Sad_Dram_Rule_6, Sad_Dram_Rule_7
45
Sad_Interleave_List_0, Sad_Interleave_List_1
46
Sad_Interleave_List_2, Sad_Interleave_List_3
46
Sad_Interleave_List_4, Sad_Interleave_List_5
46
Sad_Interleave_List_6, Sad_Interleave_List_7
46
Intel QPI Link Registers
47
Qpi_Qpilcl_L0, Qpi_Qpilcl_L1
47
Integrated Memory Controller Control Registers
47
Mc_Control
47
Mc_Status
49
Mc_Smi_Spare_Dimm_Error_Status
50
Mc_Smi_Spare_Cntrl
51
Mc_Reset_Control
51
Mc_Channel_Mapper
52
Mc_Max_Dod
53
Mc_Rd_Crdt_Init
54
Mc_Crdt_Wr_Thld
55
Mc_Scrubaddr_Lo
55
Mc_Scrubaddr_Hi
56
TAD - Target Address Decoder Registers
57
Tad_Dram_Rule_0, Tad_Dram_Rule_1
57
Tad_Dram_Rule_2, Tad_Dram_Rule_3
57
Tad_Dram_Rule_4, Tad_Dram_Rule_5
57
Tad_Dram_Rule_6, Tad_Dram_Rule_7
57
Tad_Interleave_List_0, Tad_Interleave_List_1
58
Tad_Interleave_List_2, Tad_Interleave_List_3
58
Tad_Interleave_List_4, Tad_Interleave_List_5
58
Tad_Interleave_List_6, Tad_Interleave_List_7
58
Integrated Memory Controller Channel Control Registers
59
Mc_Channel_0_Dimm_Reset_Cmd
59
Mc_Channel_1_Dimm_Reset_Cmd
59
Mc_Channel_2_Dimm_Reset_Cmd
59
Mc_Channel_0_Dimm_Init_Cmd
60
Mc_Channel_1_Dimm_Init_Cmd
60
Mc_Channel_2_Dimm_Init_Cmd
60
Mc_Channel_0_Dimm_Init_Params
61
Mc_Channel_1_Dimm_Init_Params
61
Mc_Channel_2_Dimm_Init_Params
61
Mc_Channel_0_Dimm_Init_Status
62
Mc_Channel_1_Dimm_Init_Status
62
Mc_Channel_2_Dimm_Init_Status
62
Mc_Channel_0_Ddr3Cmd
63
Mc_Channel_1_Ddr3Cmd
63
Mc_Channel_2_Ddr3Cmd
63
Mc_Channel_0_Refresh_Throttle_Support
64
Mc_Channel_1_Refresh_Throttle_Support
64
Mc_Channel_2_Refresh_Throttle_Support
64
Mc_Channel_0_Mrs_Value_0_1
64
Mc_Channel_1_Mrs_Value_0_1
64
Mc_Channel_2_Mrs_Value_0_1
64
Mc_Channel_0_Mrs_Value_2
65
Mc_Channel_1_Mrs_Value_2
65
Mc_Channel_2_Mrs_Value_2
65
Mc_Channel_0_Rank_Present
65
Mc_Channel_1_Rank_Present
65
Mc_Channel_2_Rank_Present
65
Mc_Channel_0_Rank_Timing_A Mc_Channel_1_Rank_Timing_A Mc_Channel_2_Rank_Timing_A
66
Mc_Channel_0_Rank_Timing_B Mc_Channel_1_Rank_Timing_B Mc_Channel_2_Rank_Timing_B
69
Mc_Channel_0_Bank_Timing
70
Mc_Channel_1_Bank_Timing
70
Mc_Channel_2_Bank_Timing
70
Mc_Channel_0_Refresh_Timing
70
Mc_Channel_1_Refresh_Timing
70
Mc_Channel_2_Refresh_Timing
70
Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing
71
Mc_Channel_2_Cke_Timing
71
Mc_Channel_0_Zq_Timing
71
Mc_Channel_2_Zq_Timing
71
Mc_Channel_0_Rcomp_Params
72
Mc_Channel_1_Rcomp_Params
72
Mc_Channel_2_Rcomp_Params
72
Mc_Channel_0_Odt_Params1
72
Mc_Channel_1_Odt_Params1
72
Mc_Channel_2_Odt_Params1
72
Mc_Channel_0_Odt_Params2
73
Mc_Channel_1_Odt_Params2
73
Mc_Channel_2_Odt_Params2
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Rd Mc_Channel_1_Odt_Matrix_Rank_0_3_Rd Mc_Channel_2_Odt_Matrix_Rank_0_3_Rd
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Wr Mc_Channel_1_Odt_Matrix_Rank_0_3_Wr Mc_Channel_2_Odt_Matrix_Rank_0_3_Wr
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Rd Mc_Channel_1_Odt_Matrix_Rank_4_7_Rd Mc_Channel_2_Odt_Matrix_Rank_4_7_Rd
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Wr Mc_Channel_1_Odt_Matrix_Rank_4_7_Wr Mc_Channel_2_Odt_Matrix_Rank_4_7_Wr
74
Mc_Channel_0_Waq_Params
75
Mc_Channel_1_Waq_Params
75
Mc_Channel_2_Waq_Params
75
Mc_Channel_0_Maintenance_Ops
76
Mc_Channel_0_Scheduler_Params
76
Mc_Channel_1_Maintenance_Ops
76
Mc_Channel_1_Scheduler_Params
76
Mc_Channel_2_Maintenance_Ops
76
Mc_Channel_2_Scheduler_Params
76
Mc_Channel_0_Rx_Bgf_Settings
77
Mc_Channel_0_Tx_Bg_Settings
77
Mc_Channel_1_Tx_Bg_Settings
77
Mc_Channel_2_Rx_Bgf_Settings
77
Mc_Channel_2_Tx_Bg_Settings
77
Mc_Channel_0_Ew_Bgf_Offset_Settings
78
Mc_Channel_0_Ew_Bgf_Settings
78
Mc_Channel_0_Round_Trip_Latency
78
Mc_Channel_1_Ew_Bgf_Offset_Settings
78
Mc_Channel_1_Ew_Bgf_Settings
78
Mc_Channel_1_Round_Trip_Latency
78
Mc_Channel_2_Ew_Bgf_Offset_Settings
78
Mc_Channel_2_Ew_Bgf_Settings
78
Mc_Channel_2_Round_Trip_Latency
78
Mc_Channel_0_Pagetable_Params1
79
Mc_Channel_0_Pagetable_Params2
79
Mc_Channel_1_Pagetable_Params1
79
Mc_Channel_1_Pagetable_Params2
79
Mc_Channel_2_Pagetable_Params1
79
Mc_Channel_2_Pagetable_Params2
79
Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch0
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch1
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch2
80
Mc_Tx_Bg_Data_Offset_Settings_Ch0
80
Mc_Tx_Bg_Data_Offset_Settings_Ch1
80
Mc_Tx_Bg_Data_Offset_Settings_Ch2
80
Mc_Channel_0_Addr_Match
81
Mc_Channel_1_Addr_Match
81
Mc_Channel_2_Addr_Match
81
Mc_Channel_0_Ecc_Error_Inject
82
Mc_Channel_0_Ecc_Error_Mask
82
Mc_Channel_1_Ecc_Error_Inject
82
Mc_Channel_1_Ecc_Error_Mask
82
Mc_Channel_2_Ecc_Error_Inject
82
Mc_Channel_2_Ecc_Error_Mask
82
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INTEL I7-900 DEKSTOP SPECIFICATION Datasheet (96 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 0.7 MB
Table of Contents
Table of Contents
3
Revision History
8
1 Introduction
9
High-Level View of Processor Interfaces
9
Terminology
10
References
11
2 Electrical Specifications
13
Intel ® QPI Differential Signaling
13
Power and Ground Lands
13
Decoupling Guidelines
13
Active ODT for a Differential Link Example
13
VCC, VTTA, VTTD, VDDQ Decoupling
14
Processor Clocking (BCLK_DP, BCLK_DN)
14
PLL Power Supply
14
Voltage Identification (VID)
14
Voltage Identification Definition
15
Reserved or Unused Signals
17
Market Segment Selection Truth Table for MS_ID[2:0]
17
Signal Groups
18
Test Access Port (TAP) Connection
19
Signals with ODT
19
Platform Environmental Control Interface (PECI) DC Specifications
20
DC Characteristics
20
PECI DC Electrical Limits
20
Input Device Hysteresis
21
Absolute Maximum and Minimum Ratings
21
Processor DC Specifications
22
Processor Absolute Minimum and Maximum Ratings
22
DC Voltage and Current Specification
23
Technology
23
Voltage and Current Specifications
23
VCC Static and Transient Tolerance Load Lines
25
VTT Static and Transient Tolerance Load Line
27
VTT Static and Transient Tolerance
27
DDR3 Signal Group DC Specifications
27
RESET# Signal DC Specifications
28
TAP Signal Group DC Specifications
28
PWRGOOD Signal Group DC Specifications
28
VCC Overshoot Specification
29
Control Sideband Signal Group DC Specifications
29
Die Voltage Validation
30
VCC Overshoot Example Waveform
30
3 Package Mechanical Specifications
31
Package Mechanical Drawing
31
Processor Package Assembly Sketch
31
Processor Package Drawing (Sheet 1 of 2)
32
Processor Package Drawing (Sheet 2 of 2)
33
Processor Component Keep-Out Zones
34
Package Loading Specifications
34
Package Handling Guidelines
34
Package Insertion Specifications
34
Processor Loading Specifications
34
Processor Mass Specification
35
Processor Materials
35
Processor Markings
35
Processor Top-Side Markings
35
Processor Land Coordinates
36
Processor Land Coordinates and Quadrants (Bottom View)
36
4 Land Listing
37
Land Listing by Land Name
37
Land Listing by Land Number
52
5 Signal Descriptions
67
Signal Definitions
67
6 Thermal Specifications
71
Package Thermal Specifications
71
Processor Thermal Specifications
72
Processor Thermal Profile
73
Thermal Metrology
75
Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location
75
Processor Thermal Features
76
Processor Temperature
76
Adaptive Thermal Monitor
76
Frequency and Voltage Ordering
77
THERMTRIP# Signal
79
Platform Environment Control Interface (PECI)
79
Introduction
79
Fan Speed Control with Digital Thermal Sensor
80
PECI Specifications
81
Supported PECI Command Functions and Codes
81
Gettemp0() Error Codes
81
Storage Conditions Specifications
82
Storage Conditions
82
7 Features
83
Power-On Configuration (POC)
83
Clock Control and Low Power States
83
Power on Configuration Signal Options
83
Thread and Core Power State Descriptions
84
Power States
84
Coordination of Thread Power States at the Core Level
84
Package Power State Descriptions
85
Sleep States
86
ACPI P-States (Intel Turbo Boost Technology)
86
Processor S-States
86
Enhanced Intel Speedstep Technology
87
8 Boxed Processor Specifications
89
Introduction
89
Mechanical Representation of the Boxed Processor
89
Mechanical Specifications
90
Boxed Processor Cooling Solution Dimensions
90
Space Requirements for the Boxed Processor (Side View)
90
Space Requirements for the Boxed Processor (Top View)
91
Space Requirements for the Boxed Processor (Overall View)
91
Boxed Processor Fan Heatsink Weight
92
Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
92
Electrical Requirements
92
Fan Heatsink Power Supply
92
Boxed Processor Fan Heatsink Power Cable Connector Description
92
Thermal Specifications
93
Boxed Processor Cooling Requirements
93
Baseboard Power Header Placement Relative to Processor Socket
93
Fan Heatsink Power and Signal Specifications
93
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)
94
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)
94
Variable Speed Fan
95
Boxed Processor Fan Heatsink Set Points
95
Fan Heatsink Power and Signal Specifications
95
INTEL I7-900 DEKSTOP SPECIFICATION Specification (68 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 0.47 MB
Table of Contents
Table of Contents
3
Preface
5
Summary Tables of Changes
7
Identification Information
17
Errata
19
Specification Changes
66
Specification Clarifications
67
Documentation Changes
68
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