After Comma Realignment; Fpga Rx Interface; Functional Description; Interface Width Configuration - Xilinx Virtex-6 FPGA User Manual

After Comma Realignment

When set to TRUE, RX_EN_REALIGN_RESET_BUF enables automatic reset of the RX
elastic buffer during comma realignment.

FPGA RX Interface

Functional Description

The FPGA receives RX data from the GTX RX through the FPGA RX interface. Data is read
from the RXDATA port on the positive edge of RXUSRCLK2. RXDATA can be configured
to be one, two, or four bytes wide. The actual width of the port depends on the
RX_DATA_WIDTH attribute and RXDEC8B10BUSE port settings. Port widths can be 8, 10,
16, 20, 32, and 40 bits.
The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line
rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. In
some operating modes, a second parallel clock (RXUSRCLK) must be provided for the
internal PCS logic in the receiver. This section shows how to drive the parallel clocks and
explains the constraints on those clocks for correct operation. The highest receiver data
rates require a 4-byte interface to achieve an RXUSRCLK2 rate in the specified operating
range.

Interface Width Configuration

The Virtex-6 FPGA GTX transceiver contains an internal 2-byte datapath. The FPGA
interface width is configurable by setting the RX_DATA_WIDTH attribute. When the
8B/10B decoder is enabled, the FPGA interface must be configured to 10, 20, or 40 bits.
When the 8B/10B decoder is bypassed, the FPGA interface is configured to any of the
available widths: 8, 10, 16, 20, 32, and 40 bits.
the RX datapath is selected. 8B/10B decoding is described in more detail in
Decoder, page
Table 4-56: FPGA RX Interface Datapath Configuration
RXDEC8B10BUSE
1
0
When the 8B/10B decoder is bypassed and the RX_DATA_WIDTH is 10, 20, or 40, the
RXDISPERR and RXCHARISK ports are used to extend the RXDATA port from 8 to 10 bits,
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
228.
RX_DATA_WIDTH
10
20
40
8
10
16
20
32
40
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Table 4-56 shows how the interface width for
FPGA Interface Width
8 bits
16 bits
32 bits
8 bits
10 bits
16 bits
20 bits
32 bits
40 bits
FPGA RX Interface
RX 8B/10B
Internal Data Width
20 bits
20 bits
20 bits
16 bits
20 bits
16 bits
20 bits
16 bits
20 bits
269