Rx Interface - Xilinx Virtex UltraScale+ FPGAs User Manual

RX Interface

The RX interface is the gateway to the RX datapath of the GTM transceiver. Applications receive
data through the GTM transceiver by reading data to the RXDATA port on the positive edge of
RXUSRCLK2. Port widths can be 64 and 128 bits for NRZ mode, or 80, 128, 160, and 256 bits
for PAM4 mode. The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the
RX line rate and the width of the RXDATA port. A second parallel clock (RXUSRCLK) must be
provided for the internal PCS logic in the receiver. This section shows how to drive the parallel
clocks and explains the constraints on those clocks for correct operation.
Interface Width Configuration
The GTM transceiver contains a 64-bit internal datapath in NRZ mode, and an 80-bit and 128-bit
internal datapath in PAM4 mode that is configurable by setting the TX_INT_DATA_WIDTH
attribute. When the FEC is enabled, only the 80-bit internal datapath can be used. The interface
width is configurable by setting the TX_DATA_WIDTH attribute. In NRZ mode,
TX_DATA_WIDTH can be configured to 64 or 128 bits. In PAM4 mode, TX_DATA_WIDTH can
be configured to 80, 128, 160, or 256 bits. When the FEC is enabled, only the 80-bit or 160-bit
RX internal data width can be selected.
The following table shows how the interface width for RX datapath is selected.
Table 69: RX Interface Datapath Configuration
Encod FEC
ing Allowed?
NRZ No
No
PAM4 Yes
Yes
No
No
The following figure shows the RX data received.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
RX_DATA_WIDTH RX Data Width
Encoding Selection
0
2
1
3
2
4
RX_INT_DATA_WID
TH Encoding
64 0
128 0
80 1
160 1
128 2
256 2
Send Feedback
Chapter 4: Receiver
RX Internal
Datapath
Selection
64
64
80
80
128
128
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