Table 2.6.2 Contents Of Timers 3 And 4 When Reset Or When Executing Stp Instruction - Renesas 7200 Series User Manual

2.6.2 Timer 3 and timer 4 when reset and when executing the STP instruction
Timers 3 and 4 start counting down immediately after reset status is released or stop mode is released,
and CPU starts operating by supplying the internal clock φ at overflow of these timers. Therefore, the
program can start under a stable clock.
(1) When reset
When reset, Timers 3 and 4 are automatically set by hardware as shown in Table 2.6.2, and immediately
start counting down. The counting is continued, then, Timer 4 overflows and the internal clock φ is
supplied (the internal reset is released). The program can start again.
(2) When executing the STP instruction
Immediately after the STP instruction is executed, Timers 3 and 4 are automatically set as shown
in Table 2.6.2 as in the case of reset and placed in the stop mode. When the stop mode is entered,
the processor stops supplying the internal clock φ , and contents of Timers 3 and 4 are retained.
When the stop mode is released by reset input or external interrupt input, the processor simultaneously
supplies f(X ), and Timers 3 and 4 start counting down.
IN
The counting is continued, then, when timer 4 overflows and the internal clock φ is supplied. The
program can start again.

Table 2.6.2 Contents of timers 3 and 4 when reset or when executing STP instruction

Contents
Value
Count source
Note: When executing the STP instruction, f(X
source. Accordingly, set bit 0 of the timer 34 mode register (address 00F5
the STP instruction select (f(X
FUNCTIONAL DESCRIPTION
Timer 3
FF
16
f(X )/16
IN
(except when executing the STP instructions)
IN
)/16 is selected as the timer 3 count source).
IN
7220 Group User's Manual
)/16 is not automatically selected as the timer 3 count
2.6 Timers
Timer 4
07
16
Timer 3 overflow signal
) to "0" before executing
16
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