Cpu2 Breakpoint Unit (Bpu); Bpu Control Register (Bpu_Ctrlr) - ST STM32WL5 Series Reference Manual

Debug support (DBG)
Table 286. CPU2 ROM table register map and reset values (continued)
Offset Register name
C2ROM2_PIDR2
0xFE8
Reset value
C2ROM2_PIDR3
0xFEC
Reset value
C2ROM2_CIDR0
0xFF0
Reset value
C2ROM2_CIDR1
0xFF4
Reset value
C2ROM2_CIDR2
0xFF8
Reset value
C2ROM2_CIDR3
0xFFC
Reset value
Refer to
38.14

CPU2 breakpoint unit (BPU)

The BPU allows hardware breakpoints to be set. It contains eight comparators which
monitor the instruction fetch address and return a breakpoint instruction when a match is
detected.The CPU2 PBU does not support Flash memory patch functionality.
38.14.1

BPU control register (BPU_CTRLR)

Address offset: 0x000
Reset value: 0x0000 0080
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res.
r r r
1440/1461
Section 38.13: CPU2 ROM tables
27 26 25
Res. Res. Res.
11 10 9
NUM_LIT[3:0]
r r r
for the register boundary addresses.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
NUM_CODE[3:0]
r r r r
RM0453 Rev 1
0 0 0 0
REVAND[3:0] CMOD[3:0]
0 0 0 0
PREAMBLE[7:0]
0 0 0 0
CLASS[3:0]
0 0 0 1
PREAMBLE[19:12]
0 0 0 0
PREAMBLE[27:20]
1 0 1 1
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res.
KEY
r rw
RM0453
1 0 1 1
0 0 0 0
1 1 0 1
PREAMBLE
[11:8]
0 0 0 0
0 1 0 1
0 0 0 1
16
Res.
0
ENABLE
rw