Table of Contents
Advertisement
RM0453
Table 285. CPU2 processor ROM table register map and reset values (continued)
Offset Register name
C2ROM1_CIDR2
0xFF8
Reset value
C2ROM1_CIDR3
0xFFC
Reset value
Refer to
38.13.12 CPU2 ROM2 memory type register (C2ROM2_MEMTYPER)
Address offset: 0xFCC
Reset value: 0x0000 0001
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SYSMEM: system memory
1: System memory present on this bus
38.13.13 CPU2 ROM2 CoreSight peripheral identity register 4
(C2ROM2_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Section 38.13: CPU2 ROM tables
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
for the register boundary addresses.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
F4KCOUNT[3:0]
r
r
RM0453 Rev 1
Debug support (DBG)
PREAMBLE[19:12]
0
0
PREAMBLE[27:20]
1
0
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
JEP106CON[3:0]
r
r
r
r
0
0
0
1
0 1
1
1
0
0
0 1
17
16
Res.
Res.
1
0
Res.
SYSMEM
r
17
16
Res.
Res.
1
0
r
r
1435/1461
1448
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers