Bpu Coresight Peripheral Identity Register 4 (Bpu_Pidr4) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

Debug support (DBG)

Bits 31:30 REPLACE[1:0]: Defines the behavior when a match occurs between the COMP field and the

instruction fetch address.

0x0: reserved

0x1: Breakpoint on lower half-word, upper half-word is unaffected.

0x2: Breakpoint on upper half-word, lower half-word is unaffected.

0x3: Breakpoint on both upper and lower half-words

Bit 29 Reserved, must be kept at reset value.

Bits 28:2 COMP[26:0]: Value to compare with address bits 28:2 of accesses to instruction code memory

(0x00000000 to 0x1FFFFFFF)

If a match occurs, the action to be taken is defined by the REPLACE field.

Bit 1 Reserved, must be kept at reset value.

Bit 0 ENABLE: comparator enable

The comparator is only enabled if both this bit and the BPU ENABLE bit in the BPU_CTRLR

BPU CoreSight peripheral identity register 4 (BPU_PIDR4)

Address offset: 0xFD0

Reset value: 0x0000 0004

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 F4KCOUNT[3:0]: register file size

0x0: Register file occupies a single 4-Kbyte region.

Bits 3:0 JEP106CON[3:0]: JEP106 continuation code

RM0453 Rev 1

F4KCOUNT[3:0]

JEP106CON[3:0]

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