Figure 7.4 Erase/Erase-Verify Flowchart - Renesas H8/36912 Series User Manual

16-bit single-chip microcomputer

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Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.

2. When WDT is in use, disable it once.

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Set block start address as verify address

H'FF dummy write to verify address

Read verify data

Verify data + all 1s ?

Increment address

Last address of block ?

All erase block erased ?

Figure 7.4 Erase/Erase-Verify Flowchart

ESU bit ← 10

End of erasing

Erase failure

Rev. 1.00, 11/03, page 107 of 376