Figure 7.4 Erase/Erase-Verify Flowchart - Renesas H8 Series Hardware Manual

Increment address
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Erase start
SWE bit ← 1
Wait 1 µs
n ← 1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
Verify data + all 1s ?
Yes
No
Last address of block ?
EV bit ← 0
Wait 4 µs
No
All erase block erased ?
Yes
SWE bit ← 0
Wait 100 µs
End of erasing

Figure 7.4 Erase/Erase-Verify Flowchart

*
No
Yes
EV bit ← 0
Wait 4µs
n ≤100 ?
Yes
SWE bit ← 0
Wait 100 µs
Erase failure
Rev. 1.00 Aug. 28, 2006 Page 111 of 400
Section 7 ROM
n ← n + 1
Yes
No
REJ09B0268-0100