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6.5.3
Erase Mode
To erase an individual flash memory block, follow the erase/erase-verify flowchart (single-block
erase) shown in figure 6.13.
The wait times (x, y, z, α, β, γ, ε, η) after bits are set or cleared in flash memory control register 1
(FLMCR1) and flash memory control register 2 (FLMCR2), and the maximum number of erase
operations (N), are shown in table 15.10 in section 15.2.6, Flash Memory Characteristics.
To perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in
the erase block register (EBR) at least (x) μs after setting the SWE bit to 1 in flash memory control
register 1 (FLMCR1). Next, set up the watchdog timer to prevent overerasing in the event of
program runaway, etc. Set a value greater than (y + z + α + β) μs as the WDT overflow period.
After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in
FLMCR2, and after the elapse of (y) μs or more, the operating mode is switched to erase mode by
setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase
time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, prewriting (setting memory data in the memory to be erased
to all 0) is not necessary before starting the erase procedure.
6.5.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least (α) μs later). The watchdog timer is cleared following the
elapse of more than (y + z + α + β) μs after being set, and the operating mode is switched to erase-
verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (y) μs or more. When the flash memory is read in this state (verify
data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) μs after the
dummy write before performing this read operation. If the read data has been erased (all 1),
execute a dummy write to the next address, and perform an erase-verify. If the read data has not
been erased, select erase mode again and repeat the erase/erase-verify sequence as before.
However, ensure that the erase/erase-verify sequence is not repeated more than (N) times.
When verification is completed, exit erase-verify mode, and wait for at least (η) μs. If erasure has
been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased
blocks, make a 1-bit setting in EBR for the flash memory block to be erased, and repeat the
erase/erase-verify sequence as before.
Rev.3.00 Jul. 19, 2007 page 143 of 532
6. ROM
REJ09B0397-0300
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