Pci Base Address Registers-Lmbar And Pcsrbar - Motorola MPC8240 User Manual

4.2.7 PCI Base Address Registers—LMBAR and PCSRBAR
Two base address registers are provided when the MPC8240 is used in the PCI agent mode:
• Local memory base address register (LMBAR)
• Peripheral control and status registers base address register (PCSRBAR)
These registers allow a host processor to configure the base addresses of the MPC8240
when the MPC8240 is being used as a PCI agent. The use of these memory spaces is
optional and therefore selectable by the processor. It is expected that the processor core
configures the local memory and enables the embedded utilities prior to the host software
being allowed to complete PCI configuration. See Chapter 3, "Address Maps," for more
information on the use of the embedded utilities and the address translation functionality of
the MPC8240.
Table 4-11 describes the bits of the LMBAR.
Table 4-11. Local Memory Base Address Register Bit Definitions—0x10
Bits Name
31–12 Inbound
memory base
address
11–4 Reserved
3 Prefetchable
2–1 Type
0 Memory
space
indicator
Table 4-12 describes the PCSRBAR.
Table 4-12. PCSR Base Address Register Bit Definitions—0x14
Bits Reset Value
msb 31–12 0x0000_0
11–0 0x000
Reset
R/W
Value
0x0000_0 R/W Indicates the base address where the inbound memory window
resides. The inbound memory window should be aligned based on
the granularity specified by the inbound window size specified in the
ITWR. Note that the EUMB area must be selected first, then the ITWR
programmed, and then the bits set. Refer to Chapter 3, "Address
Maps," for more information on the EUMB and the ATU.
All 0s R Reserved; the MPC8240 only allows a minimum of a 4-Kbyte window.
1 R Indicates that the space is prefetchable.
00 R The inbound memory window may be located anywhere within the
32-bit PCI address space.
0 R Indicates PCI memory space
R/W
R/W Indicates the PCI base address that is mapped to the runtime registers (for
example, DMA, I
R Reserved
Chapter 4. Configuration Registers
PCI Interface Configuration Registers
Description
Description
O).
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