Motorola MPC8240 User Manual page 629

write timing, 6-84
Floating-point model
FE0/FE1 bits, E-15
floating-point unit overview, 5-7
FP arithmetic instructions, D-19
FP compare instructions, D-20
FP load instructions, D-23
FP move instructions, D-23
FP multiply-add instructions, D-20
FP rounding/conversion instructions, D-20
FP store instructions, D-23
FPR0–FPR31, E-4
FPSCR instructions, D-20
FOE (flash output enable) signal, 2-23
FPM interface
address mulitplexing, 6-50
block diagram, 6-46
data interface, 6-54
DMA burst wrap, 6-61
ECC, 6-62
initialization, 6-55
organizations supported, 6-48
overview, 6-46
page mode retention, 6-61
parity, 6-61
power saving modes, 6-67
refresh timing, 6-66
RMW parity, 6-61
timing, 6-56
FPR0–FPR31 (floating-point registers), E-4
FPSCR (floating-point status and control register)
bit settings, E-6
FPSCR instructions, D-20
FRAME signal, 2-12, 7-9
FRR (feature reporting) register, 11-16
Full-power mode, 1-18, 14-4
G
G2 core, see Processor core
GCR (global configuration) register, 11-16
GNT (PCI bus grant) signal, 2-8, 7-4
GPR0–GPR31 (general purpose registers), E-4
GTBCR (global timer base count) register, 11-21
GTCCR (global timer current count) register, 11-21
GTDR (global timer destination) register, 11-23
GTVPR (global timer vector/ priority) register, 11-22
H
Hard reset
configuration pins sampled, 2-38
HRST_CPU (hard reset (processor)), 2-26, 2-26
HRST_CTRL (hard reset (peripheral logic)), 2-26
HASH1 and HASH2 registers, E-22
INDEX
HID0 (hardware implementation-dependent 0)
registers
description, 5-13, E-24
doze bit, 14-4
DPM enable bit, 14-4
nap bit, 14-5
HID1 (hardware implementation 1)
register, 5-16, E-27
HID2 (hardware implementation 2)
register, 5-17, E-28
host, 7-34
I
I/O master view, 3-3
2
I C control signals, see Signals, 2-25
2
I C interface
arbitration loss, 10-6
arbitration procedure, 10-5
clock stretching, 10-7
clock synchronization, 10-6
data transfer, 10-5
features list, 10-1
handshaking, 10-7
operation, 10-3
overview, 1-16
programming guidelines, 10-13
programming model, 10-2, 10-7
programming the I
registers
I2CADR, 10-7
I2CCR, 10-10
I2CDR, 10-13
I2CFDR, 10-8
I2CSR, 10-11
signals, 10-2
slave address transmission, 10-4
start condition, 10-4
start generation, 10-14
stop condition, 10-5
system configuration, 10-2
2
I2CADR (I C address) register, 10-7
2
I2CCR (I C control) register, 10-10
2
I2CDR (I C data) register, 10-13
2
I2CFDR (I C frequency divider) register, 10-8
2
I2CSR (I C status) register, 10-11
IABR (instruction address breakpoint register), E-23
IACK (processor interrupt acknowledge)
register, 11-27
IDSEL (ID select) signal, 2-16
IEEE 1149.1 specifications
signals, 15-21
specification compliance, 15-22
IFHPR (inbound free_FIFO head pointer)
register, 9-15
Index
2
C interface, 10-13
Index-5