Motorola MPC8240 User Manual page 28

Figure
Number
14-1 MPC8240 Peripheral Logic Power States................................................................... 14-7
15-1 Example PCI Address Attribute Signal Timing for Burst Read Operations .............. 15-4
15-2 Example PCI Address Attribute Signal Timing for Burst Write Operations.............. 15-5
15-3 64-Bit Mode, DRAM and SDRAM Physical Address for Debug .............................. 15-6
15-4 32-Bit Mode, DRAM and SDRAM Physical Address for Debug .............................. 15-7
15-5 64-Bit Mode, ROM and Flash Physical Address for Debug ...................................... 15-7
15-6 32-Bit Mode, ROM and Flash Physical Address for Debug ...................................... 15-7
15-7 8-Bit Mode, ROM and Flash Physical Address for Debug ........................................ 15-7
15-8 Example FPM Debug Address, MIV, and MAA Timings for Burst Read Operation 15-9
15-9 Example FPM Debug Address, MIV, and MAA Timings for Burst Write Operation15-10
15-10 Example EDO Debug Address, MIV, and MAA Timings for Burst Read Operation15-11
15-11 Example EDO Debug Address, MIV, and MAA Timings for Burst Write Operation15-12
15-12 Example SDRAM Debug Address, MIV,
and MAA Timings for Burst Read Operation........................................................... 15-13
15-13 Example SDRAM Debug Address, MIV,
and MAA Timings for Burst Write Operation.......................................................... 15-14
15-14 Example ROM Debug Address, MIV, and MAA Timings For Burst Read............. 15-15
15-15 Example Flash Debug Address, MIV, and MAA Timings For Single-Byte Read... 15-16
15-16 Example Flash Debug Address, MIV, and MAA Timings for Write Operation...... 15-16
15-17 Functional Diagram of Memory Data Path Error Injection ...................................... 15-17
15-18 DH Error Injection Mask (MDP_ERR_INJ_MASK_DH)-
Offsets 0xF_F000, 0xF00 ......................................................................................... 15-17
15-19 DL Error Injection Mask (MDP_ERR_INJ_MASK_DL)-
Offsets 0xF_F004, 0xF04 ......................................................................................... 15-18
15-20 Parity Error Injection Mask (MDP_ERR_INJ_MASK_PAR)-
Offsets 0xF_F008, 0xF08 ......................................................................................... 15-18
15-21 DH Error Capture Monitor (MDP_ERR_CAP_MON_DH)-
Offsets 0xF_F00C, 0xF0C ........................................................................................ 15-19
15-22 DL Error Capture Monitor (MDP_ERR_CAP_MON_DL)-
Offsets 0xF_F010, 0xF10 ......................................................................................... 15-20
15-23 Parity Error Capture Monitor (MDP_ERR_CAP_MON_PAR)-
Offsets 0xF_F014, 0xF14 ......................................................................................... 15-20
15-24 JTAG Interface Block Diagram ................................................................................ 15-21
16-1 Watchpoint Facility Signal Interface .......................................................................... 16-1
16-2 Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)-
Offsets 0xF_F018, 0xF18 ........................................................................................... 16-4
16-3 Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)-
Offsets 0xF_F030, 0xF30 ........................................................................................... 16-4
16-4 Watchpoint #1 Address Trigger Register (WP1_ADDR_TRIG)-
Offsets 0xF_F01C, 0xF1C .......................................................................................... 16-5
16-5 Watchpoint #2 Address Trigger Register (WP2_ADDR_TRIG)-
Offsets 0xF_F034, 0xF34 ........................................................................................... 16-5
16-6 Bit Match Generation for Watchpoint Trigger Bit Settings........................................ 16-6
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ILLUSTRATIONS
Title
MPC8240 Integrated Processor User's Manual
Page
Number