E-1 Mpc8240 Processor Programming Model—Registers - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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USER MODEL
UISA
General-Purpose
Registers
GPR0
GPR1
GPR31
Floating-Point
Registers
FPR0
FPR1
FPR31
Condition Register
CR
Floating-Point Status
and Control Register
FPSCR
XER
XER
SPR 1
Link Register
LR
SPR 8
Count Register
CTR
SPR 9
USER MODEL
VEA
Time Base Facility
(For Reading)
TBL
TBR 268
TBU
TBR 269
.
1
These implementation–specific registers may not be supported by other PowerPC processors or processor cores.
Figure E-1. MPC8240 Processor Programming Model—Registers
SUPERVISOR MODEL—OEA
Hardware
Implementation
1
Registers
HID0
SPR 1008
HID1
SPR 1009
HID2
SPR 1011
Memory Management Registers
Instruction BAT
Registers
IBAT0U
SPR 528
IBAT0L
SPR 529
IBAT1U
SPR 530
IBAT1L
SPR 531
IBAT2U
SPR 532
IBAT2L
SPR 533
IBAT3U
SPR 534
IBAT3L
SPR 535
SDR1
SDR1
SPR 25
Data Address Register
DAR
SPRGs
SPRG0
SPRG1
SPRG2
SPRG3
Miscellaneous Registers
Time Base Facility
(For Writing)
TBL
TBU
Instruction Address
Breakpoint Register
IABR
Appendix E. Processor Core Register Summary
Configuration Registers
Machine State
Register
MSR
Data BAT Registers
DBAT0U
SPR 536
DBAT0L
SPR 537
DBAT1U
SPR 538
DBAT1L
SPR 539
DBAT2U
SPR 540
DBAT2L
SPR 541
DBAT3U
SPR 542
DBAT3L
SPR 543
Exception Handling Registers
SPR 19
SPR 272
SPR 273
SPR 274
SPR 275
SPR 284
SPR 285
1
SPR 1010
PowerPC Register Set
Processor Version
Register
PVR
SPR 287
Software Table
1
Search Registers
DMISS
SPR 976
DCMP
SPR 977
HASH1
SPR 978
HASH2
SPR 979
IMISS
SPR 980
ICMP
SPR 981
RPA
SPR 982
Segment Registers
SR0
SR1
SR15
DSISR
DSISR
SPR 18
Save and Restore Registers
SRR0
SPR 26
SRR1
SPR 27
Decrementer
DEC
SPR 22
External Access
Register (Optional)
EAR
SPR 282
E-3

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