Special-Cycle Transactions - Motorola MPC8240 User Manual

PCI Bus Transactions
The MPC8240 also provides a direct method for generating PCI interrupt-acknowledge
transactions. For address map A, processor reads to 0xBFFF_FFF0–0xBFFF_FFFF
generate PCI interrupt-acknowledge transactions. For address map B, processor reads to
any location in the address range 0xFEF0_0000–0xFEFF_FFFF generate PCI
interrupt-acknowledge transactions. Note that processor writes to these addresses cause
processor transaction errors; see Section 13.3.1.1, "Processor Transaction Error," for more
information.

7.4.6.2 Special-Cycle Transactions

The special-cycle command provides a mechanism to broadcast select messages to all
devices on the PCI bus. The special-cycle command contains no explicit destination
address but is broadcast to all PCI agents.
When the MPC8240 detects a write to the CONFIG_DATA register, it checks the enable
flag and the device number in the CONFIG_ADDR register. If the enable bit is set, the bus
number corresponds to the local PCI bus (bus number = 0x00), the device number is all 1s
(0b1_1111), the function number is all 1s (0b111), and the register number is zero
(0b00_0000), then the MPC8240 performs a special-cycle transaction on the local PCI bus.
If the bus number indicates a nonlocal PCI bus, the MPC8240 performs a type 1
configuration cycle translation, similar to any other configuration cycle for which the bus
number does not match.
Aside from the special-cycle command (C/BE[3:0] = 0b0001) the address phase contains
no other valid information. Although there is no explicit address, AD[31:0] are driven to a
stable state, and parity is generated. During the data phase, AD[31:0] contain the
special-cycle message and an optional data field. The special-cycle message is encoded on
the 16 least-significant bits (AD[15:0]); the optional data field is encoded on the
most-significant 16 lines (AD[31:16]). The special-cycle message encodings are assigned
by the PCI SIG steering committee. The current list of defined encodings are provided in
Table 7-7.
Note that the MPC8240 does not automatically issue a special-cycle message when it enters
any of its power-saving modes. It is the responsibility of software to issue the appropriate
special-cycle message, if needed.
Each receiving agent must determine whether the special-cycle message is applicable to
itself. Assertion of DEVSEL in response to a special-cycle command is not necessary. The
7-28
Table 7-7. Special-Cycle Message Encodings
AD[15:0]
0x0000
0x0001
0x0002
0x0003–0xFFFF
MPC8240 Integrated Processor User's Manual
Message
SHUTDOWN
HALT
x86 architecture-specific
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