E.1.3.5 Segment Registers - Motorola MPC8240 User Manual

PowerPC Register Set

E.1.3.5 Segment Registers

The segment registers, shown in Figure E-15, contain the segment descriptors.
T Ks Kp N 0000
0 1 2 3 4
Segment register bit settings when T = 0 are described in Table E-13.
Table E-13. Segment Register Bit Settings (T = 0)
0
1
2
3
4–7
8–31
E.1.3.6 SPRG0–SPRG3
The format of SPRG0–SPRG3 is shown in Figure E-16.
0
Table E-14 provides a description of conventional uses of SPRG0 through SPRG3.
Table E-14. Conventional Uses of SPRG0–SPRG3
Register
SPRG0 Software may load a unique physical address in this register to identify an area of memory
reserved for use by the first-level exception handler. This area must be unique for each processor
in the system.
SPRG1 This register may be used as a scratch register by the first-level exception handler to save the
content of a GPR. That GPR then can be loaded from SPRG0 and used as a base register to save
other GPRs to memory.
SPRG2 This register may be used by the operating system as needed.
SPRG3 This register may be used by the operating system as needed.
E-18
7 8
Figure E-15. Segment Register Format (T = 0)
Bits Name
T T = 0 selects this format
Ks Supervisor-state protection key
Kp User-state protection key
N No-execute protection
— Reserved
VSID Virtual segment ID
Figure E-16. SPRG0–SPRG3
MPC8240 Integrated Processor User's Manual
VSID
Description
SPRG0
SPRG1
SPRG2
SPRG3
Description
Reserved
31
31