Motorola MPC8240 User Manual page 365

Table 8-3. DMR Field Descriptions—Offsets 0x100, 0x200 (Continued)
Reset
Bits Name
Value
11–10 PRC 00
9 — 0
8 EIE 0
7 EOTIE 0
6–4 — 000
3 DL 0
2 CTM 0
1 CC 0
0 CS 0
R/W
RW PCI Read Command. Indicates the types of PCI read command to be used.
00 PCI Read
01 PCI Read-line
10 PCI Read-multiple
11 Reserved
R Reserved
RW Error interrupt enable. Interrupt mechanism used depends on the setting of the
IRQS bit.
0 Disables error interrupts
1 Generates an interrupt to the processor core, through the internal int
mechanism and the EPIC unit, if there is a memory or PCI error during a DMA
transfer (signalled by the setting of LME or PE in the DSR).
RW End-of-transfer interrupt enable. Interrupt mechanism used depends on the
setting of the IRQS bit.
0 Disables end-of-transfer interrupts
1 Generates an interrupt at the completion of a DMA transfer. (that is,
NDAR[EOTD] bit is set). For chained DMA, the interrupt is driven active at the
end of the last segment. For periodic DMA, the interrupt is driven at the end of
each periodic transfer event.
R Reserved
RW Descriptor location
0 The descriptor is located in the local memory space.
1 The descriptor is located in the PCI memory space.
RW Channel transfer mode
0 Chaining mode. See Section 8.3.2, "DMA Chaining Mode."
1 Direct DMA mode. Software is responsible for placing all the required
parameters into the necessary registers to start the DMA process. See
Section 8.3.1, "DMA Direct Mode."
RW Channel continue. This bit applies only to chaining mode and is cleared by the
MPC8240 after every descriptor read. It is typically set after software dynamically
adds more descriptors to a chain that is currently in progress or to a finished
chain. Note that it is not advisable to remove descriptors by setting this bit
because there is no deterministic way to predict when the DMA controller will
read a specific descriptor.
0 Channel stopped
1 The DMA transfer will restart the transferring process starting at the current
descriptor address (in CDAR).
RW Channel start. This bit is toggled by software.
0 to 1 transition when the channel is not busy (DSR[CB] = 0) starts the DMA
process. If the channel is busy and a 0 to 1 transition occurs, then the DMA
channel restarts from a previous halt condition.
1 to 0 transition when the channel is busy (DSR[CB] = 1) halts the DMA process.
Note that in chaining mode, it is not necessary to halt the channel to modify a
descriptor because descriptors can be modified by setting the DMR[CC] bit.
Nothing happens if the channel is not busy and a 1 to 0 transition occurs.
Chapter 8. DMA Controller
DMA Register Descriptions
Description
8-17