Motorola MPC8240 User Manual page 621

Exclusive state. EMI state (E) in which only one caching device contains
Execution synchronization. All instructions in execution are architecturally
Flush. An operation that causes a modified cache block to be invalidated and
F
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Instruction queue. A holding place for instructions fetched from the current
I
Integer unit. The functional unit in the 603e responsible for executing all
Interrupt. An external signal that causes the 603e to suspend current
Invalid state. EMI state (I) that indicates that the cache block does not
K
Kill. An operation that causes a cache block to be invalidated.
L
Latency. The number of clock cycles necessary to execute an instruction and
Little-endian. A byte-ordering method in memory where the address n of a
Low-drop-out.A term used to describe linear power supplies that supply a
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M
Memory-mapped accesses. Accesses whose addresses use the segmented or
Memory coherency. Refers to memory agreement between caches and
data that is also in system memory.
complete before beginning execution (appearing to begin execution)
of the next instruction. Similar to context synchronization but doesn't
force the contents of the instruction buffers to be deleted and
refetched.
the data to be written to memory.
instruction stream.
integer instructions.
execution and take a predefined exception.
contain valid data.
make ready the results of that instruction.
word corresponds to the least significant byte. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3
being the most significant byte.
stable output even when the V
block address translation mechanisms provided by the MMU and
that occur externally with the bus protocol defined for memory.
system memory (for example, EMI cache coherency).
Glossary of Terms and Abbreviations
-V difference is low.
in out
Glossary-3