Sdram Memory Data Interface - Motorola MPC8240 User Manual

Table 6-7. SDRAM Address Multiplexing SDBA[1:0]
msb
Row x Col x Bank
0-2
11x8x4 SDRAS
or
12x8x4
SDCAS

6.2.3 SDRAM Memory Data Interface

To reduce loading on the data bus, the MPC8240 features on-chip buffers between the
internal processor core data bus and the memory data bus. The MPC8240 supports three
types of internal data path buffering for the SDRAM data interface—flow-through,
registered, and in-line buffer mode. Flow-through buffer mode is the default mode for the
MPC8240.
Table 6-8 lists the parameters that determine the data path buffer mode and also control the
parity or ECC operation of the MPC8240.
RAM_TYPE
EDO
PCKEN
WRITE _PARITY_CHK
INLINE_RD_EN
INLINE_PAR_NOT_ECC
BUF_TYPE[0]
BUF_TYPE[1]
RMW_PAR
ECC_EN
MEM_PARITY_ECC_EN
MB_ECC_ERR_EN
Table 6-9 describes the parameter settings for the available SDRAM data path buffer
options. Note that configuration register bit settings that are not specified in Table 6-9 have
undefined behavior.
and SDMA[12:0]—64-Bit Mode (Continued)
1
3 4 5 6 7 8 9
0
1 B B 1
1 A A 0
1 0
B B
A A
1 0
Table 6-8. Memory Data Path Parameters
Bit Name
Chapter 6. MPC8240 Memory Interface
Physical Address
1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9
9 8 7 6 5 4 3 2 1 0
Register and Bit Number
Offset in Register
MCCR1 @F0
MCCR2 @F4
MCCR1 @F0
MCCR2 @F4
MCCR2 @F4
MCCR2 @F4
MCCR4 @FC
MCCR4 @FC
MCCR2 @F4
MCCR2 @F4
ErrEnR1 @C0
ErrEnR2 @C4
SDRAM Interface Operation
2 2 2 2 2 2 2 2 2
0 1 2 3 4 5 6 7 8
7 6 5 4 3 2 1 0
17
16
16
19
18
20
22
20
0
17
2
3
lsb
2 3 3
9 0 1
6-13