Motorola MPC8240 User Manual page 20

Paragraph
Number
14.3.2.4.1
14.3.2.4.2
14.3.2.4.3
14.4 Example Code Sequence for Entering Processor
and Peripheral Logic Sleep Modes ............................................................. 14-11
15.1 Debug Register Summary ................................................................................. 15-1
15.2 Address Attribute Signals ................................................................................. 15-2
15.2.1 Memory Address Attribute Signals (MAA[0:2]).......................................... 15-2
15.2.2 Memory Address Attribute Signal Timing ................................................... 15-3
15.2.3 PCI Address Attribute Signals...................................................................... 15-3
15.2.4 PCI Address Attribute Signal Timing........................................................... 15-4
15.3 Memory Debug Address ................................................................................... 15-5
15.3.1 Enabling Debug Address .............................................................................. 15-5
15.3.2 Debug Address Signal Definitions ............................................................... 15-6
15.3.3 Physical Address Mappings.......................................................................... 15-6
15.3.4 RAS Encoding .............................................................................................. 15-7
15.3.5 Debug Address Timing................................................................................. 15-8
15.4 Memory Interface Valid (MIV) ........................................................................ 15-8
15.4.1 MIV Signal Timing....................................................................................... 15-9
15.5 Memory Data Path Error Injection/Capture.................................................... 15-17
15.5.1 Memory Data Path Error Injection Mask Registers.................................... 15-17
15.5.1.1 DH Error Injection Mask Register.......................................................... 15-17
15.5.1.2 DL Error Injection Mask Register .......................................................... 15-18
15.5.1.3 Parity Error Injection Mask Register ...................................................... 15-18
15.5.2 Memory Data Path Error Capture Monitor Registers................................. 15-19
15.5.2.1 DH Error Capture Monitor Register ....................................................... 15-19
15.5.2.2 DL Error Capture Monitor Register ....................................................... 15-20
15.5.2.3 Parity Error Capture Monitor Register ................................................... 15-20
15.6 JTAG/Testing Support .................................................................................... 15-21
15.6.1 JTAG Signals.............................................................................................. 15-21
15.6.2 JTAG Registers and Scan Chains ............................................................... 15-22
15.6.2.1 Bypass Register ...................................................................................... 15-22
15.6.2.2 Boundary-Scan Registers........................................................................ 15-22
15.6.2.3 Instruction Register................................................................................. 15-22
15.6.2.4 TAP Controller ....................................................................................... 15-22
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CONTENTS
System Memory Refresh during Sleep Mode..................................... 14-11
Disabling the PLL during Sleep Mode ............................................... 14-11
SDRAM Paging during Sleep Mode .................................................. 14-11
Chapter 15
Debug Features
MPC8240 Integrated Processor User's Manual
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