Watchpoint Control Mask Register Bit Field Definitions - Motorola MPC8240 User Manual

0000_00
31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-8. Watchpoint #2 Control Mask Register (WP2_CNTL_MASK)—
Table 16-5 shows the bit definitions for WP1_CNTL_MASK and WP2_CNTL_MASK.
Table 16-5. Watchpoint Control Mask Register Bit Field Definitions
Bits Name Reset Value
31–25 — 0b000_000
24 QACK_ 0
23 BR_ 0
22 BG_ 0
21 TS_ 0
20–16 TT[0:4] 0b0_0000
15 TBST_ 0
14–12 TSIZ[0:2] 0b000
11 GBL_ 0
10 CI_ 0
9 WT_ 0
8–7 TC[0:1] 0b00
6 AACK_ 0
5 ARTRY_ 0
4 DBG_ 0
3 TA_
2 TEA_
TT0[0:4]
Offsets 0xF_F038, 0xF38
R/W
R Reserved
R/W 0 Ignore QACK_ trigger bit in WPx_CNTL_TRIG.
1 Compare QACK on peripheral logic bus with WPx_CNTL_TRIG bit.
RW 0 Ignore BR_ trigger bit in WPx_CNTL_TRIG
1 Compare BR on peripheral logic bus with WPx_CNTL_TRIG bit
RW 0 Ignore BG_ trigger bit in WPx_CNTL_TRIG
1 Compare BG on peripheral logic bus with WPx_CNTL_TRIG bit
R/W 0 Ignore TS_ trigger bit in WPx_CNTL_TRIG.
1 Compare TS on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W Trigger mask for peripheral logic address transfer attribute
R/W 0 Ignore TBST_ trigger bit in WPx_CNTL_TRIG.
1 Compare TBST on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W Trigger mask for peripheral logic transfer size
R/W 0 Ignore GBL_ trigger bit in WPx_CNTL_TRIG,
1 Compare GBL on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W 0 Ignore CI_ trigger bit in WPx_CNTL_TRIG.
1 Compare CI on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W 0 Ignore WT_ trigger bit in WPx_CNTL_TRIG.
1 Compare WT on peripheral logic bus with WPx_CNTL_TRIG bit.
RW Trigger mask for peripheral logic Transfer Code
R/W 0 Ignore AACK_ trigger bit in WPx_CNTL_TRIG.
1 Compare AACK on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W 0 Ignore ARTRY_ trigger bit in WPx_CNTL_TRIG.
1 Compare ARTRY on peripheral logic bus with WPx_CNTL_TRIG bit.
R/W 0 Ignore DBG_ trigger bit in WPx_CNTL_TRIG.
1 Compare DBG on peripheral logic bus with WPx_CNTL_TRIG bit.
0 R/W 0 Ignore TA_ trigger bit in WPx_CNTL_TRIG.
1 Compare TA on peripheral logic bus with WPx_CNTL_TRIG bit.
0 R/W 0 Ignore TEA_ trigger bit in WPx_CNTL_TRIG.
1 Compare TEA on peripheral logic bus with WPx_CNTL_TRIG bit.
Chapter 16. Programmable I/O and Watchpoint
TSIZ[0:2]
9 8 7
Description
Watchpoint Registers
6 5 4 3 2 1 0
16-7