Motorola MPC8240 User Manual page 211

Table 5-8. Exceptions and Conditions (Continued)
Exception Vector Offset
Type (hex)
Alignment 00600
Program 00700
Floating-point 00800
unavailable
Decrementer 00900
Reserved 00A00–00BFF
System call 00C00
Trace 00D00
Floating-point 00E00
assist
Reserved 00E10–00FFF
Instruction 01000
translation
miss
Data load 01100
translation
miss
An alignment exception is caused when the processor core cannot perform a
memory access for any of the reasons described below:
• •The operand of a floating-point load or store is to a direct-store segment.
• •The operand of a floating-point load or store is not word-aligned.
• •The operand of a lmw, stmw, lwarx, or stwcx. is not word-aligned.
• •The operand of an elementary, multiple or string load or store crosses a
segment boundary with a change to the direct store T bit.
• •The operand of dcbz instruction is in memory that is write-through required
• or caching inhibited, or dcbz is executed in an implementation that has
either no data cache or a write-through data cache.
• •A misaligned eciwx or ecowx instruction
• •A multiple or string access with MSR[LE] set
The processor core differs from MPC603e in that it initiates an alignment exception
when it detects a misaligned eciwx or ecowx instruction and does not initiate an
alignment exception when a little-endian access is misaligned.
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• •Illegal instruction—An illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the processor core), or when execution of an
optional instruction not provided in the processor core is attempted (these do
not include those optional instructions that are treated as no-ops).
• •Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the processor core, this
exception is generated for mtspr or mfspr with an invalid SPR field if
SPR[0] = 1 and MSR[PR] = 1. This may not be true for all PowerPC
processors.
• •Trap—A trap type program exception is generated when any of the conditions
specified in a trap instruction are met.
A floating-point unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-point load, store, and move instructions)
when the floating-point available bit is cleared (MSR[FP] = 0).
The decrementer exception occurs when the most significant bit of the decrementer
(DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
—
A system call exception occurs when a System Call (sc) instruction is executed.
A trace exception is taken when MSR[SE] = 1 or when the currently completing
instruction is a branch and MSR[BE] = 1.
The MPC8420 does not generate an exception to this vector. Other PowerPC
processors may use this vector for floating-point assist exceptions.
—
An instruction translation miss exception is caused when the effective address for
an instruction fetch cannot be translated by the ITLB.
A data load translation miss exception is caused when the effective address for a
data load operation cannot be translated by the DTLB.
Chapter 5. PowerPC Processor Core
Causing Conditions
Exception Model
5-29