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The MPC8240 can be configured to support ROM/Flash devices located on the memory bus
or on the PCI bus. The RCS0 signal is sampled at reset to determine the location of
ROM/Flash. If the system ROM space is mapped to the PCI bus, the MPC8240 directs all
system ROM accesses to the PCI bus.
The MPC8240 also supports splitting the system ROM space between PCI and the memory
bus. The entire ROM space is mapped to the PCI space, and then, by setting the
configuration parameter PICR2[CF_FF0_LOCAL], the lower half of the ROM space
(0xFF00_0000–0xFF7F_FFFF) is remapped onto the memory bus. This allows the system
to have the upper half of ROM space on the PCI bus for boot firmware and the lower half of
the ROM space on the memory bus for performance critical firmware. The ROM/Flash on
the memory bus is selected by RCS1. The data path width (32 or 64 bits) is determined by
the state of the FOE and MDL[0] signals, at power on reset, as shown in Table 6-26.
6.4.1 ROM/Flash Address Multiplexing
System software must configure the MPC8240 at power-on-reset to multiplex appropriately
the row and column address bits for each bank. Address multiplexing for the 8-bit mode
occurs according to the interface configuration settings as shown in Figure 6-52.
MPC8240
Output
Signals
8-bit Mode
SDMA
SDBA
PAR
SDMA
Logical
Names
AR
Figure 6-52. ROM/Flash Address Multiplexing—8-Bit Mode
Address multiplexing for the 32-bit mode occurs according to the interface configuration
settings as shown in Figure 6-53.
1
1
1
1
0–10
1
2
3
4
0 1 2 3 4 5 6 7
1
2
2
1
1
1
0
9
8
7
Chapter 6. MPC8240 Memory Interface
ROM/Flash Interface Operation
Physical Address
1
1
1
1
1
2
2
2
5
6
7
8
9
0
1
2
1
9 8 7 6 5 4 3 2 1 0
0
0
1
1
1
1
1
1
1
9 8 7 6 5 4 3 2 1 0
6
5
4
3
2
1
0
2
2
2
2
2
2
2
3
3
4
5
6
7
8
9
0
3
1
6-77
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