Motorola MPC8240 User Manual page 631

big-endian mode,four-byte transfe, B-3
burst operation, 7-9
bus arbitration, 1-14, 7-4
bus commands, 7-9
bus error signals, 13-4
bus protocol, 7-8
bus transactions, see PCI interface
byte alignment, 7-13, B-2
byte ordering, 7-2, B-1
C/BEn signals, 7-31
cache wrap mode, 7-12
configuration cycles
configuration header, 7-22
direct access method, 7-26
type 0 and 1 accesses, 7-23
configuration space addressing, 7-13
data transfers, 7-9, 7-14, 7-33
error detection and reporting, 7-30, 13-4, 13-9
error transactions, 7-30
exclusive access, 7-29
fast back-to-back transactions, 7-21
features list, 1-12
I/O space addressing, 7-12
linear incrementing, 7-12
little-endian mode, see PCI interface, B-9
master-abort transaction termination, 13-10
master-initiated transaction termination, 7-17
memory space addressing, 7-12
MPC8240
MPC8240 as PCI bus master, 7-2
MPC8240 as PCI target, 7-3
nonmaskable interrupt, 13-11
overview, 1-14, 7-1, 7-1
PCI commands, see PCI interface, PCI
commands
PCI Local Bus Specification, xliii, 4-10, 4-10
PCI System Design Guide, xliii
PCI/local memory buffers, 12-6
PCI-to-ISA bridge, 13-5, 13-5
PCI-to-local memory read buffer (PCMRB), 12-7
PCI-to-local memory write buffers
(PCMWBs), 12-8
processor-to-PCI-read buffer (PRPRB), 12-4
processor-to-PCI-write buffers (PRPWBs), 12-5
read transactions, 7-14
registers, see Registers, PCI interface
retry PCI transactions, 7-18
signals, see Signals, PCI interface
target-abort error, 7-18, 13-10
target-disconnect, 7-2, 7-18, 12-4
target-initiated termination, 7-18
transaction termination, 7-17
turnaround cycle, 7-14
write transactions, 7-16
processor interface
INDEX
bus error signals, 13-3
byte ordering, B-1
configuration registers, 4-29
error detection, 13-6
error handling registers, 4-33
local memory buffer, 12-3
PCI buffers, 12-4
processor bus error status register, 13-6
programmable parameters
PICR1/PICR2 registers, 4-29
unsupported bus transactions error, 13-6
SDRAM interface
power-on initialization, 6-16
Internal control
arbitration
in-order execution, 12-9
out-of-order execution, 12-1
internal buffers, 12-1
Interrupt protocol, EPIC unit, 11-7
IPHPR (inbound post_FIFO head pointer)
register, 9-16
IPR (interrupt pending) register, 11-9
IPTPR (inbound post_FIFO tail pointer) register, 9-17
IRDY (initiator ready) signal, 2-12, 7-9
IRQn (discrete interrupt), 2-23
IRR (interrupt request register) register, 11-10
IS (interrupt selector) register, 11-9
ISR (in-service) register, 11-10
ITWR (inbound translation window) register, 3-15
J
JTAG interface
block diagram of JTAG interface, 15-21
JTAG signals, 15-21
registers
boundary-scan registers, 15-22
bypass register, 15-22
description, 15-22
instruction register, 15-22
status register, 15-22
TAP controller, 15-22
L
L_INT (local interrupt) signal, 2-24
Little-endian mode
accessing configuration registers, 4-2
aligned scalars, address modification, B-6
byte lane translation, B-6
byte ordering, B-5
DMA descriptors, 8-14
LE_MODE bit, 4-31, B-5
PCI bus, B-1
PCI I/O space, B-12
Index Index-7