Motorola MPC8240 User Manual page 6

Paragraph
Number
1.7.4 Error Injection/Capture on Data Path ........................................................... 1-20
1.7.5 IEEE 1149.1 (JTAG)/Test Interface ............................................................. 1-20
2.1 Signal Overview.................................................................................................. 2-1
2.1.1 Signal Cross Reference................................................................................... 2-4
2.1.2 Output Signal States during Reset .................................................................. 2-6
2.2 Detailed Signal Descriptions............................................................................... 2-7
2.2.1 PCI Interface Signals ...................................................................................... 2-7
2.2.1.1 PCI Bus Request (REQ[4:0])-Input ......................................................... 2-8
2.2.1.1.1
2.2.1.1.2
2.2.1.2 PCI Bus Grant (GNT[4:0])-Output .......................................................... 2-8
2.2.1.2.1
2.2.1.2.2
2.2.1.3 PCI Address/Data Bus (AD[31:0]) ............................................................. 2-9
2.2.1.3.1
2.2.1.3.2
2.2.1.4 Parity (PAR) ............................................................................................. 2-10
2.2.1.4.1
2.2.1.4.2
2.2.1.5 Command/Byte Enable (C/BE[3:0])......................................................... 2-10
2.2.1.5.1
2.2.1.5.2
2.2.1.6 Device Select (DEVSEL) ......................................................................... 2-11
2.2.1.6.1
2.2.1.6.2
2.2.1.7 Frame (FRAME)....................................................................................... 2-12
2.2.1.7.1
2.2.1.7.2
2.2.1.8 Initiator Ready (IRDY) ............................................................................. 2-12
2.2.1.8.1
2.2.1.8.2
2.2.1.9 Lock (LOCK)-Input ............................................................................... 2-13
2.2.1.10 Target Ready (TRDY) .............................................................................. 2-13
2.2.1.10.1
2.2.1.10.2
2.2.1.11 Parity Error (PERR).................................................................................. 2-14
2.2.1.11.1
2.2.1.11.2
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CONTENTS
Chapter 2
Signal Descriptions and Clocking
PCI Bus Request (REQ[4:0])-Internal Arbiter Enabled ...................... 2-8
PCI Bus Request (REQ[4:0])-Internal Arbiter Disabled ..................... 2-8
PCI Bus Grant (GNT[4:0])-Internal Arbiter Enabled .......................... 2-8
PCI Bus Grant (GNT[4:0])-Internal Arbiter Disabled......................... 2-9
Address/Data (AD[31:0])-Output ........................................................ 2-9
Address/Data (AD[31:0])-Input........................................................... 2-9
Parity (PAR)-Output .......................................................................... 2-10
Parity (PAR)-Input............................................................................. 2-10
Command/Byte Enable (C/BE[3:0])-Output ..................................... 2-10
Command/Byte Enable (C/BE[3:0])-Input ........................................ 2-11
Device Select (DEVSEL)-Output ...................................................... 2-11
Device Select (DEVSEL)-Input......................................................... 2-12
Frame (FRAME)-Output ................................................................... 2-12
Frame (FRAME)-Input ...................................................................... 2-12
Initiator Ready (IRDY)-Output.......................................................... 2-12
Initiator Ready (IRDY)-Input............................................................. 2-13
Target Ready (TRDY)-Output ........................................................... 2-13
Target Ready (TRDY)-Input.............................................................. 2-14
Parity Error (PERR)-Output .............................................................. 2-14
Parity Error (PERR)-Input ................................................................. 2-14
MPC8240 Integrated Processor User's Manual
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