Bit Settings For Error Enabling Register 2 (Errenr2)—0Xc4 - Motorola MPC8240 User Manual

Error Handling Registers
Table 4-33 describes the bits for ErrEnR2.
PCI SERR Enable
PCI Address Parity Error Enable
Table 4-33. Bit Settings for Error Enabling Register 2 (ErrEnR2)—0xC4
Bits Name
7 PCI address parity
error enable
6–4 —
3 ECC multi-bit error
enable
2 Processor memory
write parity error
enable
1 PCI received target
abort error enable
0 Flash ROM write error
enable
4-38
0 0
7 6 5
Reset
Value
0 This bit controls whether the MPC8240 asserts MCP (provided MCP is
enabled) if an address parity error is detected by the MPC8240 acting as a
PCI target.
0 PCI address parity errors disabled
1 PCI address parity errors enabled
000 Reserved
0 This bit enables the detection of ECC multibit errors.
0 ECC multi-bit error detection disabled
1 ECC multi-bit error detection enabled
0 This bit enables the detection of processor memory write parity errors.
(note: applies only for SDRAM with in-line parity checking).
0 Processor memory write error detection disabled
1 Processor memory write error detection enabled
0 This bit enables the detection of target abort errors received by the PCI
interface.
0 Target abort error detection disabled
1 Target abort error detection enabled
0 This bit controls whether the MPC8240 detects attempts to write to Flash
when either PICR1[FLASH_WR_EN] = 0 or
PICR2[FLASH_WR_LOCKOUT] = 0.
0 Disabled
1 Enabled
MPC8240 Integrated Processor User's Manual
4 3 2 1 0
Description
Reserved
ECC Multibit Error Enable
Processor/Memory Write
Parity Error Enable
PCI Received Target Abort
Error Enable
Flash ROM Write Error
Enable