Sdram Mode-Set Command Timing - Motorola MPC8240 User Manual

SDRAM Interface Operation

6.2.8.1 SDRAM Mode-Set Command Timing

The MPC8240 transfers the mode register data, (CAS latency, burst length, and burst type)
stored in MCCR4[SDMODE] to the SDRAM array by issuing the mode-set command
when MCCR1[MEMGO] is set. The timing of the mode-set command is shown in
Figure 6-14.
SDRAM
CLK[0:3]
CKE
CS
SDRAS
SDCAS
ADDR
WE
DQM[0:7]
DATA
Figure 6-14. SDRAM Mode Register Set Timing
6.2.9 SDRAM Parity and RMW Parity
When configured for SDRAM, the MPC8240 supports two forms of parity checking and
generation—normal parity and read-modify-write (RMW) parity. Normal parity assumes
that each of the eight parity bits is controlled by a separate DQM signal. Thus, for a
single-beat write to system memory, the MPC8240 generates a parity bit for each byte
written to memory.
RMW parity assumes that all eight parity bits are controlled by a single DQM signal;
therefore, all parity bits must be written as a single 8-bit quantity (byte). For any system
memory write operations smaller than a double word, the MPC8240 must latch the write
data, read a double word (64 bits), check the parity of that double word, merge it with the
write data, regenerate parity for the new double word, and finally write the new double word
back to memory.
6-26
MODE REGISTER DATA
(Tri-stated)
MPC8240 Integrated Processor User's Manual
Mode set to any command
Refresh or activate
Fixed at 5 clock cycles
ROW