Fpm Or Edo Dram Refresh - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
Figure 6-43 shows a single-beat write operation.
MCLK
RAS
CAS
ADDR
DRAM DATA
INTERNAL
DATA BUS
TA
WE
Figure 6-43. DRAM Single-Beat Write Timing with RMW or ECC Enabled

6.3.10 FPM or EDO DRAM Refresh

The MPC8240's memory interface distributes CAS-before-RAS (CBR) refreshes to
DRAM according to the interval specified in the MCCR2[REFINT] parameter. MCCR2
must be programmed by boot code at system start-up. The value to be stored in REFINT
represents the number of memory clock cycles required between CBR refreshes.
This value should allow for a potential collision between memory access and refresh. (The
per row refresh interval should be reduced by the longest memory access time.) For
example, for a DRAM with a cell refresh time of 64 mS and 4096 rows, the per row refresh
interval would be 64 mS/4,096 rows = 15.6 µS. If the memory interface runs at 66 MHz,
15.6 µS represents 1,030 memory clock cycles. If a burst read is in progress when a refresh
is to be performed, the refresh waits for the read to complete. Thus, the per-row refresh
interval (1,030 clocks) should be reduced by the longest access time (based on
configuration parameters) and then stored to REFINT (as a binary representation of the
difference).
6.3.10.1 FPM or EDO Refresh Timing
The refresh timing for DRAM is controlled through MCCR3[RAS
initialized during reset and controls the RAS active time during a CBR refresh. (Refer to
interval RAS in Figure 6-44.) As shown in the figure, the MPC8240 implements bank
6P
staggering for CBR refreshes. System software is responsible for optimal configuration of
interval RAS after system start-up. Such configuration must be completed before
6P
attempting access to DRAM.
6-66
ROW
WR
Device driving data bus
MPC8240 Integrated Processor User's Manual
COL
RD WR
RD WR
DRAM MPC8240
]. This register is
6P