Message Register Descriptions - Motorola MPC8240 User Manual

9.2.2 Message Register Descriptions

The IMRs allow a remote host or PCI master to write a 32-bit value that automatically
generates an interrupt to the processor core through the EPIC unit. The OMRs allow the
processor core to write an outbound message that automatically causes the outbound
interrupt signal INTA to be asserted on the PCI bus. These interrupts can be masked in the
IMIMR and OMIMR. When the message registers are written, their corresponding
interrupt status bits in the IMISR and OMISR are set. Figure 9-1 shows the bits of the IMRs
and OMRs.
.
31
Figure 9-1. Message Registers (IMRs and OMRs)
Table 9-3 shows the bits settings for the IMRs and OMRs.
Table 9-3. IMR and OMR Field Descriptions—Offsets 0x050–0x05C,
Bits Name Reset Value
31–0 MSG Undefined
9.2.3 Doorbell Register Descriptions
The IDBR allows a remote processor to set a bit in the register from the PCI bus. This, in
turn, generates an interrupt to the processor core through the EPIC unit if the interrupt is
not masked in IMIMR, or generates mcp (if it is not masked in IMIMR). After the local
interrupt (or mcp) is generated, it can only be cleared by the processor core by writing a 1
to the bits that are set in the IDBR. The remote processor can only generate the local
interrupt through the IDBR; it cannot clear the interrupt. Figure 9-2 shows the IDBR.
MC
31 30
0x0_0050–0x0_005C
R/W
R/W The inbound and outbound message registers contain generic message
data to be passed between the processor core and remote processors.
Figure 9-2. Inbound Doorbell Register (IDBR)
Chapter 9. Message Unit (with I
Message and Doorbell Register Programming Model
MSG
Description
DBn
O)
2
0
0
9-3