Motorola MPC8240 User Manual page 171

PCKEN
RAM_TYPE
SREN
MEMGO
BURST
DBUS_SIZ[0–1]
ROMNAL ROMFAL
31 28 27
Figure 4-29. Memory Control Configuration Register 1 (MCCR1)—0xF0
Bits Name
31–28 ROMNAL
27–23 ROMFAL
22–21 DBUS_SIZ[0–1]
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Table 4-38. Bit Settings for MCCR1—0xF0
Reset
Value
All 1s For burst-mode ROM and Flash reads, ROMNAL controls the next access time.
The maximum value is 0b1111 (15). The actual cycle count is three cycles more
than the binary value of ROMNAL.
For Flash writes, ROMNAL measures the write pulse recovery (high) time. The
maximum value is 0b1111 (15). The actual cycle count is four cycles more than
the binary value of ROMNAL.
All 1s For nonburst ROM and Flash reads, ROMFAL controls the access time. For
burst-mode ROMs, ROMFAL controls the first access time. The maximum value
is 0b11111 (31). For the 64-bit and 32-bit configurations, the actual cycle count
is three cycles more than the binary value of ROMFAL. For the 8-bit
configuration, the actual cycle count is two cycles more than the binary value of
ROMFAL.
For Flash writes, ROMFAL measures the write pulse low time. The maximum
value is 0b11111 (31). The actual cycle count is two cycles more than the binary
value of ROMFAL.
xx Read-only. This field indicates the state of the ROM bank 0 data path width
configuration signals [DL[0], FOE] at reset as follows.
For ROM/Flash chip select #0 (RCSO),
00 32-bit data bus.
x1 8-bit data bus.
10 64-bit data bus.
For ROM/Flash chip select #1 (RCS1) and (S)DRAM,
0x 32-bit data bus.
For FPM/EDO systems only, (RAM_TYPE=1).
1x 64-bit data bus.
Chapter 4. Configuration Registers
Memory Control Configuration Registers
8 7 6 5
Description
Bank 7 Row
Bank 6 Row
Bank 5 Row
Bank 4 Row
Bank 3 Row
Bank 2 Row
Bank 1 Row
Bank 0
Row
4 3 2 1 0
4-43