Programmable Processor Power Modes - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
Table of Contents

Advertisement

any machine check exception. Also, negation of QACK (controlled by the peripheral
logic block) causes the processor core to wake up from nap mode. A return to
full-power state from a nap state occurs within four processor clock cycles
• Processor sleep—Sleep mode reduces power consumption to a minimum by
disabling all internal functional units, after which external logic can disable the PLL
and the internal sys_logic_clk signal. The MPC8240 returns to the full-power state
from sleep mode upon receipt of an interrupt (signalled by the assertion of int), a
system management interrupt, a hard or soft reset, or any machine check exception.
Also, negation of QACK (controlled by the peripheral logic block) causes the
processor core to wake up from sleep mode.
The external system logic must enable the processor PLL and the internal
sys_logic_clk signal before any of the wake-up events occur. Refer to
Section 14.3.2.4.2, "Disabling the PLL during Sleep Mode," for more information
on how the PLLs are locked and Section 2.3, "Clocking," for more information on
the clock signals of the MPC8240.
Note that the processor core cannot switch from one power management mode to another
without first returning to full-on mode. Table 14-1 summarizes the four power states for the
processor.
Table 14-1. Programmable Processor Power Modes
PM Mode
Functioning Units
Full power
All units active
Full power
Requested logic by
demand
(with DPM)
Doze
Bus snooping
Data cache as needed
Decrementer timer
Nap
Decrementer timer
Sleep
None
Activation Method
By instruction dispatch
Controlled by software
(write to HID0)
Controlled by software
(write to HID0) and
qualified with QACK
from peripheral logic
Controlled by software
(write to HID0) and
qualified with QACK
from peripheral logic
Chapter 14. Power Management
Processor Core Power Management
Full-Power Wake Up Method
External asynchronous exceptions
(assertion of SMI or int)
Decrementer exception
Hard or soft reset
Machine check exception (mcp)
External asynchronous exceptions
(assertion of SMI, or int)
Decrementer exception
Negation of QACK by peripheral logic
Hard or soft reset
Machine check exception (mcp)
External asynchronous exceptions
(assertion of SMI, or int)
Negation of QACK by peripheral logic
Hard or soft reset
Machine check exception (mcp)
14-3

Advertisement

Table of Contents
loading

Table of Contents