Motorola MPC8240 User Manual page 13

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7.1.2 The MPC8240 as a PCI Target ....................................................................... 7-3
7.1.3 PCI Signal Output Hold Timing ..................................................................... 7-3
7.2 PCI Bus Arbitration ............................................................................................ 7-4
7.2.1 Internal Arbitration for PCI Bus Access......................................................... 7-4
7.2.1.1 Processor-Initiated Transactions to PCI Bus .............................................. 7-5
7.2.1.2 DMA-Initiated Transactions to the PCI Bus .............................................. 7-5
7.2.2 PCI Bus Arbiter Operation ............................................................................. 7-6
7.2.3 PCI Bus Parking.............................................................................................. 7-7
7.2.4 Power-Saving Modes and the PCI Arbiter ..................................................... 7-8
7.2.5 Broken Master Lock-Out ................................................................................ 7-8
7.3 PCI Bus Protocol................................................................................................ 7-8
7.3.1 Basic Transfer Control.................................................................................... 7-9
7.3.2 PCI Bus Commands........................................................................................ 7-9
7.3.3 Addressing .................................................................................................... 7-11
7.3.3.1 Memory Space Addressing....................................................................... 7-12
7.3.3.2 I/O Space Addressing ............................................................................... 7-12
7.3.3.3 Configuration Space Addressing .............................................................. 7-13
7.3.4 Device Selection ........................................................................................... 7-13
7.3.5 Byte Alignment............................................................................................. 7-13
7.3.6 Bus Driving and Turnaround ........................................................................ 7-14
7.4 PCI Bus Transactions........................................................................................ 7-14
7.4.1 PCI Read Transactions.................................................................................. 7-14
7.4.2 PCI Write Transactions................................................................................. 7-16
7.4.3 Transaction Termination............................................................................... 7-17
7.4.3.1 Master-Initiated Termination.................................................................... 7-17
7.4.3.2 Target-Initiated Termination .................................................................... 7-18
7.4.4 Fast Back-to-Back Transactions ................................................................... 7-21
7.4.5 Configuration Cycles .................................................................................... 7-21
7.4.5.1 The PCI Configuration Space Header ...................................................... 7-21
7.4.5.2 Accessing the PCI Configuration Space................................................... 7-23
7.4.5.2.1
7.4.5.2.2
7.4.6 Other Bus Transactions................................................................................. 7-27
7.4.6.1 Interrupt-Acknowledge Transactions ....................................................... 7-27
7.4.6.2 Special-Cycle Transactions ...................................................................... 7-28
7.5 Exclusive Access .............................................................................................. 7-29
7.5.1 Starting an Exclusive Access........................................................................ 7-29
7.5.2 Continuing an Exclusive Access................................................................... 7-29
7.5.3 Completing an Exclusive Access.................................................................. 7-30
7.5.4 Attempting to Access a Locked Target......................................................... 7-30
7.5.5 Exclusive Access and the MPC8240 ............................................................ 7-30
7.6 PCI Error Functions .......................................................................................... 7-30
7.6.1 PCI Parity...................................................................................................... 7-31
CONTENTS
Type 0 Configuration Translation ........................................................ 7-25
Type 1 Configuration Translation ........................................................ 7-27
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