Motorola MPC8240 User Manual page 426

Programming Guidelines
Most EPIC control and status registers are readable and return the last value written. The
exceptions to this rule are as follows:
• EOI register, which returns zeros on reads
• Activity bit (A) of the vector/priority registers, which returns the value according to
the status of the current interrupt source
• IACK register, which returns the vector of highest priority that is currently pending,
or the spurious vector.
• Reserved bits, which normally return 0
Even though reserved fields return 0, this should not be assumed by the programmer.
Reserved bits should always be written with the value they returned when read. Thus the
registers with reserved fields should be programmed by reading the value, modifying the
appropriate fields, and writing back the value.
The following guidelines are recommended when the EPIC unit is programmed in mixed
mode (GCR[M] = 1):
• If the processor's memory management unit (MMU) is enabled, all EPIC registers
must be located in a cache-inhibited and guarded area.
• The EPIC portion of the embedded utilities memory block (EUMB) must be set up
appropriately. (Registers within the EUMB are located from 0x8000_0000 to
0xFDFF_FFFF.)
• The EPIC registers are described in this chapter in little-endian format. If the system
is in big-endian mode, the bytes must be appropriately swapped by software.
In addition, the following initialization sequence is recommended:
1. Write the vector, priority and polarity values in each interrupt's vector/priority
register leaving their M (mask) bit set. This is only required for interrupts to be used.
2. Set the processor current task priority register (PCTPR) value to zero.
3. Program the EPIC to mixed mode by setting GCR[M] = 1.
4. If using direct mode, set EICR[SIE] = 0. Otherwise, to use serial mode, program the
S_CLK ratio field in EICR[R] for the desired interrupt frequency, and set EICR[SIE]
= 1.
5. Clear the M bit in the vector/priority registers to be used.
6. Perform a software loop to clear all pending interrupts:
— Load counter with FPR[NIRQ].
— While (counter > 0), perform IACK and EOI's to guarantee all the interrupt
pending and in-service registers are cleared.
7. Set the PCTPR value to desired priority.
11-14 MPC8240 Integrated Processor User's Manual